JPS6252330B2 - - Google Patents

Info

Publication number
JPS6252330B2
JPS6252330B2 JP55131278A JP13127880A JPS6252330B2 JP S6252330 B2 JPS6252330 B2 JP S6252330B2 JP 55131278 A JP55131278 A JP 55131278A JP 13127880 A JP13127880 A JP 13127880A JP S6252330 B2 JPS6252330 B2 JP S6252330B2
Authority
JP
Japan
Prior art keywords
data
point data
floating
point
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55131278A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5755447A (en
Inventor
Haruyasu Ito
Akisuke Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55131278A priority Critical patent/JPS5755447A/ja
Publication of JPS5755447A publication Critical patent/JPS5755447A/ja
Publication of JPS6252330B2 publication Critical patent/JPS6252330B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
JP55131278A 1980-09-20 1980-09-20 Data converting circuit Granted JPS5755447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55131278A JPS5755447A (en) 1980-09-20 1980-09-20 Data converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55131278A JPS5755447A (en) 1980-09-20 1980-09-20 Data converting circuit

Publications (2)

Publication Number Publication Date
JPS5755447A JPS5755447A (en) 1982-04-02
JPS6252330B2 true JPS6252330B2 (en]) 1987-11-05

Family

ID=15054192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55131278A Granted JPS5755447A (en) 1980-09-20 1980-09-20 Data converting circuit

Country Status (1)

Country Link
JP (1) JPS5755447A (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5924342A (ja) * 1982-07-30 1984-02-08 Hitachi Ltd 演算装置

Also Published As

Publication number Publication date
JPS5755447A (en) 1982-04-02

Similar Documents

Publication Publication Date Title
US5282153A (en) Arithmetic logic unit
EP0127988B1 (en) A normalizing circuit
JP2662196B2 (ja) 演算結果正規化方法及び装置
JP2674754B2 (ja) バレル・シフタ
US5862065A (en) Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer
US5497341A (en) Sign-extension of immediate constants in an ALU using an adder in an integer logic unit
US5469377A (en) Floating point computing device for simplifying procedures accompanying addition or subtraction by detecting whether all of the bits of the digits of the mantissa are 0 or 1
JPS6097435A (ja) 演算処理装置
EP0171805A2 (en) High speed digital arithmetic unit
JP3178746B2 (ja) 浮動小数点数のためのフォーマット変換装置
JPH0145649B2 (en])
EP0234495B1 (en) Arithmetic circuit capable of executing floating point operations and fixed point operations
JPH0343645B2 (en])
JPS6252330B2 (en])
GB1006868A (en) Data processing machine
EP0265948B1 (en) Data processor capable of immediately calculating branch address in relative address branch
JPS5968058A (ja) フロ−テイング乗算器
JPS59206942A (ja) 先行壱検出回路
JPH0619700B2 (ja) 演算装置
JP2842768B2 (ja) 浮動小数点演算装置
JPS6141014B2 (en])
JP3139011B2 (ja) 固定小数点プロセッサ
JPH0323937B2 (en])
JPS62154134A (ja) デ−タ変換装置
JPS6079429A (ja) 浮動小数点演算器